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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12608-2E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95140 Series MB95F146S/F146W/FV100D-101
DESCRIPTION
The MB95140 series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURE
* F2MC-8FX CPU core Instruction set optimized for controllers * Multiplication and division instructions * 16-bit arithmetic operations * Bit test branch instruction * Bit manipulation instructions etc. * Clock * Main clock * Main PLL clock * Sub clock (for dual clock product) * Sub PLL clock (for dual clock product) (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2006-2007 FUJITSU LIMITED All rights reserved
MB95140 Series
(Continued) * Timer * 8/16-bit compound timer x 2 channels * 8/16-bit PPG x 2 channels * 16-bit PPG * Timebase timer * Watch prescaler (for dual clock product) * LIN-UART * Full duplex double buffer * Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable * UART/SIO * Full duplex double buffer * Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable * External interrupt * Interrupt by edge detection (rising, falling, or both edges can be selected) * Can be used to recover from low-power consumption (standby) modes. * 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. * Low-power consumption (standby) mode * Stop mode * Sleep mode * Watch mode (for dual clock product) * Timebase timer mode * I/O port * The number of maximum ports * Single clock product : 24 ports * Dual clock product : 22 ports * Port configuration * General-purpose I/O ports (CMOS) : Single-clock product : 24 ports : Dual-clock product : 22 ports * Flash memory security function Protects the content of Flash memory (Flash memory device only)
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MB95140 Series
PRODUCT LINEUP
Part number*1 MB95F146S Parameter Type ROM capacity RAM capacity Reset output Option Clock system Low voltage detection reset Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time Single clock product : 24 ports Single clock No : 136 : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 61.5 ns (at machine clock frequency 16.25 MHz) : 0.6 s (at machine clock frequency 16.25 MHz) Dual clock product : 22 ports Flash memory product 32K bytes 1K byte No Dual clock MB95F146W
CPU functions
General purpose I/O ports Timebase timer Watchdog timer Peripheral functions Wild register
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at 4 MHz main oscillation clock) Reset generated cycle At 10 MHz main oscillation clock : Min 105 ms At 32.768 kHz sub oscillation clock (for dual clock product) : Min 250 ms Capable of replacing 3 bytes of ROM data Data transfer capable in UART/SIO Full duplex double buffer, variable data length (5/6/7/8 bits), built-in baud rate generator NRZ type transfer format, error detected function LSB-first or MSB-first can be selected. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable Dedicated reload timer allowing a wide range of communication speeds to be set. Full duplex double buffer. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable LIN functions available as the LIN master or LIN slave. 8-bit or 10-bit resolution can be selected. (Continued)
UART/SIO
LIN-UART
8/10-bit A/D converter (8 channels)
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MB95140 Series
(Continued) Part number*1 MB95F146S Parameter Each channel of the timer can be used as "8-bit timer x 2 channels" or "16-bit timer x 1 channel". 8/16-bit compound Built-in timer function, PWC function, PWM function, capture function and square wave timer (2 channels) form output Count clock : 7 internal clocks and external clock can be selected. 16-bit PPG PWM mode or one-shot mode can be selected. Counter operating clock : 8 selectable clock sources Support for external trigger start Each channel of the PPG can be used as "8-bit PPG x 2 channels" or "16-bit PPG x 1 channel". Counter operating clock : 8 selectable clock sources Count clock : 4 selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock source 1 second and setting counter value to 60) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) Interrupt by edge detection (rising, falling, or both edges can be selected.) Can be used to recover from standby modes. Supports automatic programming, Embedded AlgorithmTM *2 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Data retention time : 20 years Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash Sleep, stop, watch (for dual clock product), and timebase timer MB95F146W
8/16-bit PPG (2 channels) Peripheral functions 4 Watch counter (for dual clock product) Watch prescaler (for dual clock product) External interrupt (12 channels)
Flash memory
Standby mode
*1 : MASK ROM products are currently under consideration. *2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. Note : Part number of the evaluation device in MB95140 series is MB95FV100D-101. When using it, the MCU board (MB2146-301A) is required.
MB95140 Series
OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum value is shown as follows. Oscillation stabilization wait time (2 - 2) /FCH
14
Remarks Approx. 4.10 ms (at 4 MHz main oscillation clock)
PACKAGES AND CORRESPONDING PRODUCTS
Part number Package FPT-32P-M21 BGA-224P-M08 : Available : Unavailable MB95F146S MB95F146W MB95FV100D-101
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MB95140 Series
DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
* Notes on Using Evaluation Products The Evaluation product has not only the functions of the MB95140 series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for peripheral resources not used by the MB95140 series are therefore access-barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are used, the address may be read or written unexpectedly). Note that the values read from barred addresses are different between the Evaluation product and the Flash memory product. Therefore, the value must not be used for program. The Evaluation product does not support the functions of some bits in single-byte registers. Read/write access to these bits does not cause hardware malfunctions. The Evaluation, and Flash memory products are designed to behave completely the same way in terms of hardware and software. * Difference of Memory Spaces If the amount of memory on the Evaluation product is different from that of the Flash memory product, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to " CPU CORE". * Current Consumption For details of current consumption, refer to " ELECTRICAL CHARACTERISTICS". * Package For details of information on each package, refer to " PACKAGES AND CORRESPONDING PRODUCTS" and " PACKAGE DIMENSIONS". * Operating voltage The operating voltage is different among the Evaluation and Flash memory products. For details of operating voltage, refer to " ELECTRICAL CHARACTERISTICS" * Difference between RST and MOD pins The input type of RST and MOD pins is CMOS input on the Flash memory product.
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MB95140 Series
PIN ASSIGNMENT
(TOP VIEW)
P13/TRG0/ADTG
P07/INT07/AN07
P12/UCK0/EC0
P60/PPG10
32 31 30 29 28 27 26 25
P06/INT06/AN06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/INT01/AN01/PPG01 P00/INT00/AN00/PPG00 AVss
P61/PPG11
P14/PPG0
P11/UO0
P10/UI0
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
P62/TO10 P63/TO11 P64/EC1 RST PG1/X0A* PG2/X1A* PG0 Vcc
9 10 11 12 13 14 15 16
X0
AVcc
PF2
PF1
PF0
MOD
X1
(FPT-32P-M21) * : The pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product.
Vss
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MB95140 Series
PIN DESCRIPTION
Pin no. 1 2 Pin name P06/INT06/ AN06/TO01 P05/INT05/ AN05/TO00 P04/INT04/ AN04/SIN P03/INT03/ AN03/SOT P02/INT02/ AN02/SCK P01/INT01/ AN01/PPG01 P00/INT00/ AN00/PPG00 AVss AVcc PF2 PF1 PF0 MOD X0 X1 Vss Vcc PG0 PG2/X1A H/A 20 21 PG1/X0A RST B' B A H Operating mode designation pin Main clock input oscillation pin Main clock I/O oscillation pin Power supply pin (GND) Power supply pin General-purpose I/O port This pin is general-purpose port in single clock product (PG2) . This pin is sub clock oscillation pin in dual clock product (32 kHz) . This pin is general-purpose port in single clock product (PG1) . This pin is sub clock oscillation pin in dual clock product (32 kHz) . Reset pin (Continued) K General-purpose I/O port. Large current port. I/O circuit type* Function General-purpose I/O port. Shared with external interrupt input (INT05, INT06), A/D analog input (AN05, AN06) and 8/16-bit compound timer ch.0 output (TO00, TO01). General-purpose I/O port. Shared with external interrupt input (INT04), A/D converter analog input (AN04) and LIN-UART data input (SIN). General-purpose I/O port. Shared with external interrupt input (INT03), A/D converter analog input (AN03) and LIN-UART data output (SOT). General-purpose I/O port. Shared with external interrupt input (INT02), A/D converter analog input (AN02) and LIN-UART clock I/O (SCK). General-purpose I/O port. Shared with external interrupt input (INT00, INT01), A/D converter analog input (AN00, AN01) and 8/16-bit PPG ch.0 output (PPG00, PPG01). A/D converter power supply pin (GND) A/D converter power supply pin
D
3
E
4
D
5
D
6 7 8 9 10 11 12 13 14 15 16 17 18 19
D

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MB95140 Series
(Continued) Pin no. 22 23 24 25 26 27 Pin name P64/EC1 P63/TO11 P62/TO10 P61/PPG11 P60/PPG10 P14/PPG0 P13/TRG0/ ADTG K H K I/O circuit type* Function General-purpose I/O port. Shared with 8/16-bit compound timer ch.1 clock input. General-purpose I/O port. Shared with 8/16-bit compound timer ch.1 output. General-purpose I/O port. Shared with 8/16-bit PPG ch.1 output. General-purpose I/O port. Shared with 8/16-bit PPG ch.1 output. General-purpose I/O port. Shared with 16-bit PPG ch.0 output. General-purpose I/O port. Shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D trigger input (ADTG). General-purpose I/O port. Shared with UART/SIO ch.0 clock I/O (UCK0) and 8/16-bit compound timer ch.0 clock input (EC0). General-purpose I/O port. Shared with UART/SIO ch.0 data output. General-purpose I/O port. Shared with UART/SIO ch.0 data input. General-purpose I/O port. Shared with external interrupt input (INT07) and A/D converter analog input (AN07).
28
H
29
P12/UCK0/EC0
H
30 31
P11/UO0 P10/UI0 P07/INT07/ AN07
H G
32
D
* : For the I/O circuit type, refer to " I/O CIRCUIT TYPE".
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MB95140 Series
I/O CIRCUIT TYPE
Type Circuit Remarks * Oscillation circuit * High-speed side Feedback resistance : approx. 1 M * Low-speed side Feedback resistance : approx. 24 M (Evaluation product : approx. 10 M) Dumping resistance : approx. 144 k (Evaluation product : without dumping resistance) * Only for input * Hysteresis input Hysteresis input B' Reset input * * * * CMOS output Hysteresis input Analog input With pull - up control
X1 (X1A) X0 (X0A) N-ch
Clock input
A
Standby control
B
Mode input
R P-ch P-ch
Pull-up control Digital output Digital output Analog input
D
N-ch
A/D control Standby control External control
Hysteresis input * * * * * CMOS output CMOS input Hysteresis input Analog input With pull - up control
R P-ch P-ch
Pull-up control Digital output Digital output
N-ch
E Analog input CMOS input A/D control Standby control External control Hysteresis input (Continued)
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MB95140 Series
(Continued) Type
Circuit * * * *
Remarks CMOS output CMOS input Hysteresis input With pull - up control
R P-ch P-ch
Pull-up control Digital output Digital output CMOS input Hysteresis input
G
N-ch
Standby control
R P-ch P-ch
Pull-up control Digital output Digital output Hysteresis input
* CMOS output * Hysteresis input * With pull - up control
H
N-ch
Standby control
P-ch
* CMOS output Digital output * Hysteresis input Digital output Hysteresis input
K Standby control
N-ch
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MB95140 Series
HANDLING DEVICES
* Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AVCC) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off. * Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the VCC power-supply voltage. For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range (50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. * Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode.
PIN CONNECTION
* Treatment of Unused Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. * Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 F ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. * Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS pins near this device.
12
MB95140 Series
* Mode Pin (MOD) Connect the MOD pin directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the MOD pin to VCC or VSS pins and to provide a low-impedance connection. * Analog Power Supply Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00 to AN07 pins.
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MB95140 Series
PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER
* Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-32P-M21 TEF110-95F146 Parallel programmers AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more)
Note : For information on applicable adapter models and parallel programmers, contact the following: Flash Support Group, Inc. TEL: +81-53-428-8380 * Sector Configuration The individual sectors of Flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: Flash memory 32 Kbytes FFFFH 1FFFFH *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. * Programming Method 1) Set the type code of the parallel programmer to "1723E". 2) Load program data to programmer addresses 18000H to 1FFFFH. 3) Programmed by parallel programmer CPU address 8000H Programmer address* 18000H
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MB95140 Series
BLOCK DIAGRAM
F MC-8FX CPU RST X0, X1 PG2/(X1A)* PG1/(X0A)* PG0 Reset control Clock control Watch prescaler Watch counter P00/INT00 to P07/INT07 P10/UI0 P11/UO0 P12/UCK0 16-bit PPG Internal bus P13/TRG0/ADTG P14/PPG0 (P00/PPG00) (P01/PPG01) (P02/SCK) (P03/SOT) (P04/SIN) (P05/TO00) (P06/TO01) (P12/EC0) (P00/AN00 to P07/AN07) AVCC AVSS Port Other pins MOD, VCC, VSS Port 8/16-bit compound timer ch.0 LIN-UART 8/16-bit PPG ch.0 UART/SIO 8/16-bit compound timer ch.1 External interrupt 8/16-bit PPG ch.1 P60/PPG10 P61/PPG11 P62/TO10 P63/TO11 P64/EC1 PF0 to PF2 PG0 ROM RAM Interrupt control Wild register
2
8/10-bit A/D converter
* : The pins are general-purpose port in single clock product and sub clock oscillation pin in dual clock product.
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MB95140 Series
CPU CORE
1. Memory space
Memory space of the MB95140 series is 64K bytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose 7 registers and vector table. Memory map of the MB95140 series is shown below.
* Memory Map
MB95F146S MB95F146W 0000H I/O 0080H 0100H 0200H 0480H Access prohibited 0F80H Extended I/O 1000H Access prohibited 8000H Flash memory 60 Kbytes Flash memory 32 Kbytes 1000H 0F80H Extended I/O RAM 1 Kbyte
Register
MB95FV100D-101 0000H I/O 0080H 0100H 0200H RAM 3.75 Kbytes
Register
FFFFH
FFFFH
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MB95140 Series
2. Register
The MB95140 series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored. Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer to point to a memory address. Stack pointer (SP) : A 16-bit register to indicate a stack area. Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register
16-bit
PC A T IX EP SP PS
Initial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH 0000H 0000H 0000H 0000H 0000H 0030H
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.) * Structure of the Program Status
bit15 bit14 bit13 bit12 bit11 bit10 PS R4 R3 R2 R1 R0 DP2 bit9 DP1 bit8 DP0 bit7 H bit6 I bit5 IL1 bit4 IL0 bit3 N bit2 Z bit1 V bit0 C
RP
DP
CCR
17
MB95140 Series
The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: * Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper
"0" "0" "0" "0" "0" "0" "0" "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3
OP code lower
b2 A2 b1 A1 b0 A0
Generated address A15 A14 A13 A12 A11 A10 A9
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 000B (initial value) 001B 010B 011B 100B 101B 110B 111B 0080H to 00FFH 0000H to 007FH 0000H to 007FH (without mapping) 0080H to 00FFH (without mapping) 0100H to 017FH 0180H to 01FFH 0200H to 027FH 0280H to 02FFH 0300H to 037FH 0380H to 03FFH 0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at interrupt. : Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to "1". Interrupt is disabled when this flag is set to "0". The flag is cleared to "0" when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by these bits. IL1 0 0 1 1 N flag Z flag V flag C flag IL0 0 1 0 1 Interrupt level 0 1 2 3 Low = no interruption Priority High H flag
: Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Cleared to "0" when the
bit is set to "0".
: Set to "1" when an arithmetic operation results in "0". Cleared to "0" otherwise. : Set to "1" if the complement on 2 overflows as a result of an arithmetic operation. Cleared to "0"
otherwise. : Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. Set to the shift-out value in the case of a shift instruction.
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MB95140 Series
The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8register. Up to a total of 32 banks can be used on the MB95140 series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). * Register Bank Configuration 8-bit This address = 0100H + 8 x (RP)
Address 100H R0 R1 R2 R3 R4 R5 R6 107H R7 Bank 0 R0 R1 R2 R3 R4 R5 R6 R7 1F8H R0 R1 R2 R3 R4 R5 R6 1FFH R7 Bank 31
32 banks 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance.
Memory area
19
MB95140 Series
I/O MAP
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH to 0015H 0016H 0017H 0018H to 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH to 0034H 0035H 0036H 0037H 0038H 0039H 003AH Register abbreviation PDR0 DDR0 PDR1 DDR1 WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC PDR6 DDR6 PDRF DDRF PDRG DDRG PUL0 PUL1 PULG T01CR1 T00CR1 T11CR1 T10CR1 PC01 Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Timebase timer control register Watch prescaler control register Watchdog timer control register (Disabled) Port 6 data register Port 6 direction register (Disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register Port 1 pull-up register (Disabled) Port G pull-up register 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 8/16-bit compound timer 11 control status register 1 ch.1 8/16-bit compound timer 10 control status register 1 ch.1 8/16-bit PPG1 control register ch.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B 11111111B 00000000B 1010X011B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 20
MB95140 Series
Address 003BH 003CH 003DH 003EH to 0041H 0042H 0043H 0044H to 0047H 0048H 0049H 004AH 004BH 004CH to 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH to 006BH 006CH 006DH 006EH 006FH
Register abbreviation PC00 PC11 PC10 PCNTH0 PCNTL0 EIC00 EIC10 EIC20 EIC30 SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 TDR0 RDR0 ADC1 ADC2 ADDH ADDL
Register name 8/16-bit PPG0 control register ch.0 8/16-bit PPG1 control register ch.1 8/16-bit PPG0 control register ch.1 (Disabled) 16-bit PPG control status register (Upper byte) ch.0 16-bit PPG control status register (Lower byte) ch.0 (Disabled) External interrupt circuit control register ch.0/ch.1 External interrupt circuit control register ch.2/ch.3 External interrupt circuit control register ch.4/ch.5 External interrupt circuit control register ch.6/ch.7 (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART reception/transmission data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 ch.0 UART/SIO serial mode control register 2 ch.0 UART/SIO serial status register ch.0 UART/SIO serial output data register ch.0 UART/SIO serial input data register ch.0 (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (Upper byte) 8/10-bit A/D converter data register (Lower byte)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W
Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
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MB95140 Series
Address 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H
Register abbreviation WCSR FSR SWRE0 SWRE1 WREN WROR ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0
Register name Watch counter status register (Disabled) Flash memory status register Flash memory sector writing control register 0 Flash memory sector writing control register 1 (Disabled) Wild register address compare enable register Wild register data test setting register (Mirror of register bank pointer (RP) and direct bank pointer (DP) ) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (Upper byte) ch.0 Wild register address setting register (Lower byte) ch.0 Wild register data setting register ch.0 Wild register address setting register (Upper byte) ch.1 Wild register address setting register (Lower byte) ch.1 Wild register data setting register ch.1 Wild register address setting register (Upper byte) ch.2 Wild register address setting register (Lower byte) ch.2 Wild register data setting register ch.2 (Disabled) 8/16-bit compound timer 01 control status register 0 ch.0 8/16-bit compound timer 00 control status register 0 ch.0 8/16-bit compound timer 01 data register ch.0 8/16-bit compound timer 00 data register ch.0 8/16-bit compound timer 00/01 timer mode control register ch.0 8/16-bit compound timer 11 control status register 0 ch.1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000B 000X0000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
22
MB95140 Series
Address 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H 0FA6H to 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H to 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH 0FC0H to 0FC2H 0FC3H 0FC4H to 0FE2H Register abbreviation T10CR0 T11DR T10DR TMCR1 PPS01 PPS00 PDS01 PDS00 PPS11 PPS10 PDS11 PDS10 PPGS REVC PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 BGR1 BGR0 PSSR0 BRSR0 AIDRL Register name 8/16-bit compound timer 10 control status register 0 ch.1 8/16-bit compound timer 11 data register ch.1 8/16-bit compound timer 10 data register ch.1 8/16-bit compound timer 10/11 timer mode control register ch.1 8/16-bit PPG1 cycle setting buffer register ch.0 8/16-bit PPG0 cycle setting buffer register ch.0 8/16-bit PPG1 duty setting buffer register ch.0 8/16-bit PPG0 duty setting buffer register ch.0 8/16-bit PPG1 cycle setting buffer register ch.1 8/16-bit PPG0 cycle setting buffer register ch.1 8/16-bit PPG1 duty setting buffer register ch.1 8/16-bit PPG0 duty setting buffer register ch.1 8/16-bit PPG start register 8/16-bit PPG output inversion register (Disabled) 16-bit PPG down counter register (Upper byte) ch.0 16-bit PPG down counter register (Lower byte) ch.0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 16-bit PPG duty setting buffer register (Upper byte) ch.0 16-bit PPG duty setting buffer register (Lower byte) ch.0 (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO dedicated baud rate generator prescaler selection register ch.0 UART/SIO dedicated baud rate generator baud rate setting register ch.0 (Disabled) A/D input disable register (Lower byte) (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 23
MB95140 Series
(Continued) Address 0FE3H 0FE4H to 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation WCDR ILSR WICR Register name Watch counter data register (Disabled) Input level select register Interrupt pin control register (Disabled) R/W R/W R/W R/W Initial value 00111111B 00000000B 01000000B
* R/W access symbols R/W : Readable/Writable R : Read only W : Write only * Initial value symbols 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. Note : Do not write to the " (Disabled) ". Reading the " (Disabled) " returns an undefined value.
24
MB95140 Series
INTERRUPT SOURCE TABLE
Interrupt source External interrupt ch.0 External interrupt ch.4 External interrupt ch.1 External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 UART/SIO ch.0 8/16-bit compound timer ch.0 (Lower) 8/16-bit compound timer ch.0 (Upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch.1 (Lower) 8/16-bit PPG ch.1 (Upper) (Unused) 8/16-bit PPG ch.0 (Upper) 8/16-bit PPG ch.0 (Lower) 8/16-bit compound timer ch.1 (Upper) 16-bit PPG ch.0 (Unused) (Unused) 8/10-bit A/D converter Timebase timer Watch timer/Watch counter (Unused) 8/16-bit compound timer ch.1 (Lower) Flash memory Interrupt request number IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23 Vector table address Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) L00 [1 : 0] L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] L21 [1 : 0] L22 [1 : 0] L23 [1 : 0] Low High
25
MB95140 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage*1 Input voltage*1 Output voltage*
1
Symbol VCC AVCC VI VO ICLAMP |ICLAMP| IOL1 IOL2
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 + 2.0 20 15 15
Unit V V V mA mA mA *2 *3 *3
Remarks
Maximum clamp current Total maximum clamp current "L" level maximum output current
Applicable to pins*4 Applicable to pins*4 Other than PF0 to PF2 PF0 to PF2 Other than PF0 to PF2 Average output current = operating current x operating ratio (1 pin) PF0 to PF2 Average output current = operating current x operating ratio (1 pin)
IOLAV1 "L" level average current IOLAV2
4 mA 12
"L" level total maximum output current "L" level total average output current "H" level maximum output current
IOL IOLAV IOH1 IOH2

100
mA Total average output current = operating current x operating ratio (Total of pins) Other than PF0 to PF2 PF0 to PF2 Other than PF0 to PF2 Average output current = operating current x operating ratio (1 pin) PF0 to PF2 Average output current = operating current x operating ratio (1 pin)
50 - 15 - 15 -4
mA
mA
IOHAV1 "H" level average current IOHAV2
mA -8
"H" level total maximum output current "H" level total average output current
IOH IOHAV

- 100 - 50
mA Total average output current = operating current x operating ratio (Total of pins) (Continued)
mA
26
MB95140 Series
(Continued) Parameter Power consumption Operating temperature Storage temperature Symbol Pd TA Tstg Rating Min - 40 - 55 Max 320 + 85 + 150 Unit mW C C Remarks
*1 : The parameter is based on AVSS = VSS = 0.0 V. *2 : Apply equal potential to AVCC and VCC. *3 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Applicable to pins : P00 to P07, P10 to P14, P60 to P64, PF0 to PF2, PG0 * Use within recommended operating conditions. * Use at DC voltage (current). * The + B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. * The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this affects other devices. * Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. * Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the + B input pin open. * Sample recommended circuits : * Input/Output Equivalent Circuits Protective diode Limiting resistance
Vcc P-ch N-ch R
+ B input (0 V to 16 V)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
27
MB95140 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V) Parameter Symbol Pin name Power supply voltage VCC, AVCC Operating temperature TA Condition Value Min 2.3* 2.4* 2.6 1.5 - 40 Max 3.3 3.3 3.6 3.3 + 85 C Unit Remarks At normal operating, TA = -10 C to +85 C V At normal operating, TA = -40 C to +85 C MB95FV100D-101 TA = +5 to +35 Retain status in stop mode
* : The values vary with the operating frequency. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
28
MB95140 Series
3. DC Characteristics
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol VIH Pin name P04, P10 Conditions *1 Value Min 0.7 VCC Typ Max VCC + 0.3 Unit V Remarks At selecting CMOS input level
"H" level input voltage
P00 to P07, P10 to P14, VIHS P60 to P64, PF0 to PF2, PG0, PG1*2, PG2*2 VIHM RST, MOD VIL P04, P10
*1
0.8 VCC
VCC + 0.3
V
Hysteresis input
*1
0.8 VCC VSS - 0.3

VCC + 0.3 0.3 VCC
V V
Hysteresis input At selecting CMOS input level (Hysteresis input)
"L" level input voltage
P00 to P07, P10 to P14, VILS P60 to P64, PF0 to PF2, PG0, PG1*2, PG2*2 VILM RST, MOD
*1
VSS - 0.3
0.2 VCC
V
Hysteresis input
VSS - 0.3 2.4 2.4 -5

0.2 VCC 0.4 0.4 +5
V V V V V A
Hysteresis input
"H" level output voltage "L" level output voltage Input leakage current (Hi-Z output leakage current) Pull-up resistor
VOH1
Output pin other IOH = - 4.0 mA than PF0 to PF2 IOH = - 8.0 mA Output pin other IOL = 4.0 mA than PF0 to PF2 IOL = 12 mA 0.0 V < VI < VCC
VOH2 PF0 to PF2 VOL1
VOL2 PF0 to PF2
ILI
All input pins
When the pull-up is prohibition setting
P00 to P07, RPULL P10 to P14, PG0, VI = 0.0 V PG1*2, PG2*2 FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2) FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2)
25
50
100
k
When the pull-up is permission setting

11.0
14.0
At other than Flash mA memory writing and erasing mA At Flash memory writing and erasing
Power supply current*3
ICC
VCC (External clock operation)
30.0
35.0
17.6
22.4
At other than Flash mA memory writing and erasing mA At Flash memory writing and erasing (Continued) 29
38.1
44.9
MB95140 Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Value Conditions Unit Remarks Min Typ Max FCH = 20 MHz FMP = 10 MHz Main Sleep mode (divided by 2) FCH = 32 MHz FMP = 16 MHz Main Sleep mode (divided by 2) FCL = 32 kHz FMPL = 16 kHz Sub clock mode (divided by 2) , TA = + 25 C FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) , TA = + 25 C VCC (External clock operation) FCL = 32 kHz Watch mode Main stop mode TA = + 25 C FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) FCH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5) FCL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) , TA = + 25 C FCH = 10 MHz Timebase timer mode TA = + 25 C Sub stop mode TA = + 25 C
Parameter
Symbol
Pin name
4.5
6.0
mA
ICCS
7.2
9.6
mA
ICCL
25
35
A
ICCLS
7
15
A
Power supply current*3
ICCT
2
10
A
10
14
mA
ICCMPLL
16.0
22.4
mA
ICCSPLL
190
250
A
ICTS
0.64
0.80
mA
ICCH
1
5
A (Continued)
30
MB95140 Series
(Continued) Symbol IA Power supply
current*3
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Pin name Conditions FCH = 10 MHz At operating of A/D conversion AVCC IAH FCH = 10 MHz At stopping of A/D conversion TA = + 25 C Value Min Typ 1.3 Max 2.2 Unit Remarks
Parameter
mA
1
5
A
Input capacitance
CIN
Other than AVCC, f = 1 MHz AVSS, VCC, VSS
5
15
pF
*1 : P04, P10 can switch the input level to either the "CMOS input level" or "hysteresis input level". The switching of the input level can be set by the input level selection register (ILSR). *2 : Single clock product only *3 : Power supply current is regulated by external clock. * Refer to "4. AC Characteristics (1) Clock Timing" for FCH and FCL. * Refer to "4. AC Characteristics (2) Source Clock/Machine Clock" for FMP and FMPL.
31
MB95140 Series
4. AC Characteristics
(1) Clock Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter SymPin name Conditions bol Value Min 1.00 1.00 FCH X0, X1 3.00 3.00 Clock frequency 3.00 3.00 FCL X0A, X1A tHCYL Clock cycle time tLCYL tWH1 tWL1 tWH2 tWL2 tCR tCF X0A, X1A X0, X1 100 50 10 30.5 15.2 1000 1000 10 32.768 Typ 32.768 Max Unit Remarks When using main oscillation circuit
16.25 MHz
32.50 MHz When using external clock 10.00 MHz Main PLL multiplied by 1 8.13 6.50 4.06 MHz Main PLL multiplied by 2 MHz Main PLL multiplied by 2.5 MHz Main PLL multiplied by 4 kHz When using sub oscillation circuit
When using sub PLL kHz Flash memory product : VCC = 2.3 V to 3.3 V ns ns s ns s ns When using main oscillation circuit When using external clock When using sub oscillation circuit, When using external clock When using external clock Duty ratio is about 30% to 70%. When using external clock
Input clock pulse width Input clock rise time and fall time
X0 X0A X0, X0A
32
MB95140 Series
* Input wave form for using external clock (main clock)
tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL1
X0
* Figure of main clock input port external connection When using a crystal or ceramic oscillator
Microcontroller X0 X1 FCH C1 C2
When using external clock
Microcontroller X0 X1
Open
FCH
* Input wave form for using external clock (sub clock)
tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.1 VCC 0.1 VCC 0.1 VCC tWL2
X0A
* Figure of sub clock input port external connection When using a crystal or ceramic oscillator
Microcontroller X0A X1A FCL C1 C2
When using external clock
Microcontroller X0A X1A
Open
FCL
33
MB95140 Series
(2) Source Clock/Machine Clock (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter SymPin bol name Value Min Typ Max Unit Remarks When using main clock Min : FCH = 8.125 MHz, PLL multiplied by 2 Max : FCH = 1 MHz, divided by 2 When using sub clock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2
61.5 Source clock cycle time* (Clock before setting division)
1
2000
ns
tSCLK
7.6 61.0 s
Source clock frequency
FSP FSPL
0.5 16.384 100
16.25
MHz When using main clock When using main clock Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using sub clock Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16
131.072 kHz When using sub clock 32000 ns
Machine clock cycle time*2 (Minimum instruction execution time)
tMCLK
7.6 976.5 16.250 s
Machine clock frequency
FMP FMPL
0.031 1.024
MHz When using main clock
131.072 kHz When using sub clock
*1 : Clock before setting division due to machine clock division ratio selection bits (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bits (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follows. * Main clock divided by 2 * PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication) * Sub clock divided by 2 * PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follows. * Source clock (no division) * Source clock divided by 4 * Source clock divided by 8 * Source clock divided by 16
34
MB95140 Series
* Outline of Clock Generation Block
FCH (main oscillation) Divided by 2
Main PLL x1 x2 x 2.5 x4 SCLK (source clock) FCL (sub oscillation) Divided by 2 Clock mode select bit (SYCC: SCS1, SCS0)
Division circuit x1 x 1/4 x 1/8 x 1/16
MCLK (machine clock)
Sub PLL x2 x3 x4
35
MB95140 Series
* Operating Voltage - Operating Frequency (When TA = - 10 C to + 85 C) * MB95F146S, MB95F146W Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range
3.3 3.3
Main clock mode and main PLL mode operation guarantee range Operating voltage (V)
Operating voltage (V)
2.7 2.3
2.3
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz 5 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
* Operating Voltage - Operating Frequency (When TA = - 40 C to + 85 C) * MB95F146S, MB95F146W Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range
3.3 3.3
Main clock mode and main PLL mode operation guarantee range Operating voltage (V)
Operating voltage (V)
2.7 2.4
2.4
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz 5 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
36
MB95140 Series
* Operating voltage - Operating frequency (TA = + 5 C to + 35 C) * MB95FV100D-101 Sub PLL, sub clock mode and watch mode operation guarantee range
3.6 3.6
Main clock mode and main PLL mode operation guarantee range Operating voltage (V)
Operating voltage (V)
3.3
2.6
2.6
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range Main clock operation guarantee range
S ource clock frequency (FSPL)
Source clock frequency (FSP)
37
MB95140 Series
* Main PLL Operation Frequency
[MHz] 16.25 16
15
x4
12
Source clock frequency (FSP)
x 2.5
10
x2
x1
7.5
6
5
3
0
3
4
4.062
5
6.4
6.5
8
8.125
10 [MHz]
Machine clock frequency (FMP)
38
MB95140 Series
(3) External Reset (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter RST "L" level pulse width Symbol Value Min 2 tMCLK*1 tRSTL Oscillation time of oscillator*2 + 2 tMCLK*1 Max Unit ns ns Remarks At normal operating At stop mode, sub clock mode, sub sleep mode, and watch mode
*1 : Refer to " (2) Source Clock/Machine Clock" for tMCLK. *2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of s and several ms. In the external clock, the oscillation time is 0 ms. * At Normal Operating
tRSTL
RST
0.2 VCC 0.2 VCC
* At Stop Mode, Sub clock Mode, Sub Sleep Mode, Watch Mode, and Power-on
tRSTL 0.2 VCC 0.2 VCC
RST
90% of amplitude
X0
Internal operating clock
2 tMCLK
Oscillation time Oscillation stabilization wait time of oscillator Execute instruction Internal reset
39
MB95140 Series
(4) Power-on Reset (AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Conditions Value Min 1 Max 36 Unit ms ms Waiting time until power-on Remarks
tR 1.5 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.
VCC
1.5 V
Limiting the slope of rising within 20 mV/ms is recommended. Hold condition in stop mode
VSS
40
MB95140 Series
(5) Peripheral Input Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width Symbol
tILIH tIHIL
Pin name INT00 to INT07, EC0, EC1, TRG0/ADTG
Value Min 2 tMCLK* 2 tMCLK* Max
Unit ns ns
* : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tILIH
tIHIL
INT00 to INT07, EC0, EC1, TRG0/ADTG
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
41
MB95140 Series
(6) UART/SIO, Serial I/O Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time UCK UO time Valid UI UCK UCK valid UI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK UO time Valid UI UCK UCK valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 External clock operation output pin : CL = 80 pF + 1TTL. Conditions Internal clock operation output pin : CL = 80 pF + 1TTL. Value Min 4 tMCLK* - 190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* 0 2 tMCLK* 2 tMCLK* Max + 190 190 Unit ns ns ns ns ns ns ns ns ns
* : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
* Internal shift clock mode
tSCYC
UCK0
2.4 V 0.8 V tSLOV 0.8 V
UO0
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
UI0
0.8 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV
UCK0
UO0
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
UI0
0.8 VCC 0.2 VCC
42
MB95140 Series
(7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "L" pulse width Serial clock "H" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SCK fall time SCK rise time SymPin name bol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tIVSHE tSHIXE tF tR SCK Internal clock SCK, SOT operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK External clock SCK, SIN operation output pin : CL = 80 pF + 1 TTL. SCK, SIN SCK SCK Conditions Value Min 5 tMCLK*3 -95 tMCLK* + 190
3
Max + 95 2 tMCLK* + 95
3
Unit ns ns ns ns ns ns ns ns ns ns ns
0 3 tMCLK*3 - tR tMCLK* + 95
3
tSLOVE SCK, SOT
190 tMCLK*3 + 95
10 10
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
43
MB95140 Series
* Internal shift clock mode
tSCYC 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI
SCK
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE 0.2 VCC tR 0.8 VCC
SCK
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
44
MB95140 Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SCK fall time SCK rise time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR Pin name SCK SCK, SOT Internal clock operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK SCK, SOT External clock SCK, SIN operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK SCK Conditions Value Min 5 tMCLK*3 -95 tMCLK* + 190
3
Max + 95 2 tMCLK* + 95
3
Unit ns ns ns ns ns ns ns ns ns ns ns
0 3 tMCLK*3 - tR tMCLK*3 + 95 190 tMCLK*3 + 95
10 10
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
45
MB95140 Series
* Internal shift clock mode
tSCYC
SCK
2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI
2.4 V
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
* External shift clock mode
tSHSL tSLSH 0.8 VCC 0.2 VCC tR tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE tF 0.2 VCC
SCK
0.8 VCC
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
46
MB95140 Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SOT SCK delay time Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT Internal clock operation output pin : CL = 80 pF + 1 TTL. Conditions Value Min 5 tMCLK*3 -95 tMCLK* + 190
3
Max + 95 4 tMCLK*3
Unit ns ns ns ns ns
0
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tSCYC
SCK
0.8 V tSOVLI 2.4 V 0.8 V tIVSLI
2.4 V
tSHOVI
2.4 V 0.8 V tSLIXI 0.8 VCC 0.2 VCC
0.8 V
SOT
SIN
0.8 VCC 0.2 VCC
47
MB95140 Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time SOT SCK delay time Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI Pin name SCK SCK, SOT Internal clock SCK, SIN operating output pin : CL = 80 pF + 1 TTL. SCK, SIN Conditions Value Min 5 tMCLK*3 -95 tMCLK* + 190
3
Max + 95 4 tMCLK*3
Unit ns ns ns ns ns
0
SCK, SOT
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tSCYC
SCK
tSOVHI
2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 VCC 0.2 VCC 2.4 V 0.8 V
2.4 V
SOT
SIN
0.8 VCC 0.2 VCC
48
MB95140 Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics (AVCC = VCC = 1.8 V to 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Resolution Total error Linearity error Differential linear error Zero transition voltage Full-scale transition voltage Compare time VOT VFST Symbol Value Min - 3.0 - 2.5 - 1.9 Typ Max 10 + 3.0 + 2.5 + 1.9 Unit bit LSB LSB LSB V V V V s s s 2.7 V AVCC 3.3 V 1.8 V AVCC < 2.7 V 2.7 V AVCC 3.3 V 1.8 V AVCC < 2.7 V 2.7 V AVCC 3.3 V 1.8 V AVCC < 2.7 V 2.7 V AVCC 3.3 V external impedance < at 1.8 k 1.8 V AVCC < 2.7 V external impedance < at 14.8 k Remarks
AVSS - 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB AVSS - 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB AVCC - 3.5 LSB AVCC - 1.5 LSB AVCC + 0.5 LSB AVCC - 2.5 LSB AVCC - 0.5 LSB AVCC + 1.5 LSB 0.6 20 0.4 140 140
Sampling time
30 400 + 0.3 AVCC AVCC 600 5 s A V V A A
Analog input current Analog input voltage Reference voltage Reference voltage supply current
IAIN VAIN IR IRH
-0.3 AVSS AVSS + 1.8
AVCC pin AVCC pin, During A/D operation AVCC pin, At stop mode
49
MB95140 Series
(2) Notes on Using A/D Converter * About the external impedance of analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Analog input equivalent circuit
R
Analog input
C
Comparator
During sampling : ON 2.7 V AVCC 3.6 V 1.8 V AVCC < 2.7 V Note : The values are reference values. R 1.7 k (Max) 84 k (Max) C 14.5 pF (Max) 25.2 pF (Max)
* The relationship between external impedance and minimum sampling time (External impedance = 0 k to 100 k)
AVCC 2.7 V
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15
(External impedance = 0 k to 20 k)
AVCC 2.7 V
20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4
External impedance [k]
AVCC 1.8 V
20
25
30
35
40
External impedance [k]
Minimum sampling time [s]
Minimum sampling time [s]
* About errors As |AVCC - AVSS| becomes smaller, values of relative errors grow larger.
50
MB95140 Series
(3) Definition of A/D Converter Terms * Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") of a device and the full-scale transition point ("11 1111 1111" "11 1111 1110") compared with the actual conversion values obtained. * Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. * Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise.
Ideal I/O characteristics
VFST
Total error
3FFH 3FEH
3FFH 3FEH 1.5 LSB
Actual conversion characteristic {1 LSB x (N - 1) + 0.5 LSB}
Digital output
Digital output
3FDH
3FDH
004H 003H 002H 001H 0.5 LSB AVSS AVCC VOT 1 LSB
004H 003H 002H 001H AVSS AVCC VNT Actual conversion characteristic Ideal characteristics
Analog input 1 LSB = AVCC - AVSS 1024 (V)
Analog input
VNT - {1 LSB x (N - 1) + 0.5 LSB} Total error of = [LSB] digital output N 1 LSB
N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N.
(Continued)
51
MB95140 Series
(Continued) Zero transition error
004H
Actual conversion characteristic
Full-scale transition error
Ideal characteristics
3FFH
Digital output
003H
Ideal characteristics
Digital output
Actual conversion characteristic
3FEH
VFST
002H
Actual conversion characteristic
3FDH
(measurement value)
001H
VOT (measurement value)
Actual conversion characteristic
3FCH
AVSS
AVCC
AVSS
AVCC
Analog input
Analog input
Linearity error
3FFH 3FEH 3FDH
Actual conversion characteristic
Differential linear error
Ideal characteristics
N+1H {1 LSB x N + VOT}
VFST
(measurement value)
Actual conversion characteristic
Digital output
Digital output
V (N+1)T
NH
VNT 004H 003H 002H 001H AVSS
Actual conversion characteristic Ideal characteristics
N-1H
VNT
Actual conversion characteristic
N-2H
VOT (measurement value)
AVCC
AVSS
Analog input Linear error in = VNT - {1 LSB x N + VOT} 1 LSB digital output N
Analog input
AVCC
Differential linear error = in digital output N
V (N + 1) T - VNT 1 LSB
-1
N VNT VOT VFST
: A/D converter digital output value : A voltage at which digital output transits from (N - 1) to N. (Ideal value) = AVSS + 0.5 LSB [V] (Ideal value) = AVCC - 1.5 LSB [V]
52
MB95140 Series
6. Flash Memory Program/Erase Characteristics
Parameter Chip erase time Byte programming time Program/erase cycle Power supply voltage at program/erase Flash memory data retention time Value Min 10000 2.7 20*3 Typ 1*1 32 Max 1.5*2 3600*2 3.3 Unit s s cycle V year Average TA = +85 C Remarks Excludes 00H programming prior erasure. Excludes system-level overhead time.
*1 : TA = + 25 C, VCC = 3.0 V, 10000 cycles *2 : TA = + 85 C, VCC = 2.7 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 C) .
53
MB95140 Series
MASK OPTION
No. Part number Specifying procedure Clock mode select* * Single-system clock mode * Dual-system clock mode Low voltage detection reset* * With low voltage detection reset * Without low voltage detection reset Clock supervisor* * With clock supervisor * Without clock supervisor Selection of oscillation stabilization wait time * Selectable the initial value of main clock oscillation stabilization wait time MB95F146S Setting disabled Single-system clock mode MB95F146W Setting disabled Dual-system clock mode MB95FV100D-101 Setting disabled Changing by the switch on MCU board
1
2
No
No
No
3
No
No
No
4
Fixed to oscillation Fixed to oscillation Fixed to oscillation stabilization wait stabilization wait time stabilization wait time of (214 - 2) /FCH time of (214 - 2) /FCH of (214 - 2) /FCH
* : Low voltage detection reset and clock supervisor are options of 5-V products.
54
MB95140 Series
ORDERING INFORMATION
Part number MB95F146SPFM MB95F146WPFM MB2146-301A (MB95FV100D-101PBT) Package 32-pin plastic LQFP (FPT-32P-M21)
(
MCU board 224-pin plastic PFBGA (BGA-224P-M08)
)
55
MB95140 Series
PACKAGE DIMENSIONS
32-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference) 0.80 mm 7 x 7 mm Gullwing Plastic mold 1.70 mm MAX P-LQFP32-7x7-0.80
(FPT-32P-M21)
32-pin plastic LQFP (FPT-32P-M21)
9.000.20(.354.008)SQ
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
* 7.000.10(.276.004)SQ
24 17
0.1450.055 (.0057.0022)
25
16
Details of "A" part 0.10(.004) 1.50 -0.10
+0.20 +.008
.059 -.004
(Mounting height)
INDEX 0~8
32 9
0.25(.010)
1
8
"A" 0.20(.008)
M
0.80(.031)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.320.05 (.013.002)
C
2002 FUJITSU LIMITED F32032S-c-3-5
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
56
MB95140 Series
MAIN CHANGES IN THIS EDITION
Page Section Change Results Preliminary Data SheetData Sheet Changed the part number MB95FV100B-101MB95FV100D-101 CPU functions Minimum instruction execution time : 0.1 s (at machine clock frequency 10 MHz) Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz) Interrupt processing time : 0.9 s (at machine clock frequency 10 MHz) Interrupt processing time : 0.6 s (at machine clock frequency 16.25 MHz) Added the description Flash memory Changed under the table*3; VI1VI Changed the Min value of power supply voltage VCC, AVCC. TA = - 10 C to + 85 C 1.82.3 TA = - 40 C to + 85 C 2.02.4 Moved "H" level input voltage and "L" level input voltage from the section "2. Recommended Operating Conditions". 29, 30 3. DC Characteristics Added to FMP = 16 MHz in the section of ICC, ICCS, ICCMPLL of power supply voltage. Changed the Typ and Max values of ICTS 0.4 0.64 (Typ value) 0.5 0.80 (Max value) Changed the Max values of clock frequency X0, X1. When using main oscillation circuit 1016.25 When using external clock 2032.50 Main PLL multiplied by 2 : 58.13 Main PLL multiplied by 2.5 : 4 6.50 Added the Main PLL multiplied by 4 Changed source clock cycle time (when using main clock) Min : FCH = 10 MHz, PLL multiplied by 1 Min : FCH = 8.125 MHz, PLL multiplied by 2 34 (2) Source Clock/Machine Clock Changed the Max value of source clock frequency FSP. 1016.25 Changed machine clock cycle time (when using main clock) Min : FSP = 10 MHzMin : FSP = 16.25 MHz Changed the Max value of machine clock frequency FMP. 10 .00016.250 (Continued)
3
PRODUCT LINEUP
4 27
ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings
2. Recommended Operating Conditions
28
32
4. AC Characteristics (1) Clock Timing
57
MB95140 Series
(Continued) Page 35 36, 37 38 4. AC Characteristics (2) Source Clock/Machine Clock
Section
Change Results Changed the diagram of * Outline of Clock Generation Block Changed the diagram of * Operating voltage - Operating frequency Changed the diagram of * Main PLL operation frequency range.
49
Changed the pin name in the value section of full-scale 5. A/D Converter transition voltage; (1) A/D Converter Electrical Characteristics AVRAVCC
55
ORDERING INFORMATION
The part number is revised as follows; MB2146-301 MB2146-301A
The vertical lines marked in the left side of the page show the changes.
58
MB95140 Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
F0701

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